Gate arrays are used in VLSI integrated circuit chips to implement MOSFET circuits in semiconductor wafers. An MOS gate array consists of an array of MOS transistor sources and drains separated by channels, above which are formed gates to control the conductivity of the channels and thus the state of the transistors. An array of these gates (and their sources and drains) becomes functional only when connected by conductive wiring to appropriate other elements.
Generally, the connecting is accomplished in two steps: a library of macrocells is available to translate simple frequently used logic functions such as NAND, flip-flop, AND, multiplexer, and counter into a gate array wiring pattern, then the macrocells are connected together to form the complex logic functions of the VLSI chip.
Although conceptually there are two steps, the actual metallization to accomplish the two steps is laid out in as few layers as possible, preferably two, so the metal to implement a single macrocell and the metal to connect macrocells to each other is in the same metallization layers. Therefore if an area in a metal layer is used for connecting points within a macrocell, it is not also available for connecting macrocells to each other.
There has been considerable interest in implementing complex logic operations on smaller areas of semiconductor material, while simultaneously retaining the flexibility provided by a gate array in which identical structural units or core cells repeat throughout a large portion of the semiconductor area. A gate array structure consists generally of a base array of many active areas which can be fabricated as a standard product on which is formed one or more "personality layers" comprising conductive material to interconnect the active areas into a desired logical structure.
The personality layers reflect the function or functions to be implemented by the finished array. A given base array can be used to implement many different functions by appropriately designing the personality layers. Thus a gate array allows many different logic functions to be implemented using the same base array. The geometry of the base array cell affects the ability of the designer using later metallization to achieve a final product having maximum density and performance.
One prior art layout of a CMOS logic array required dedicated routing channels that are positioned in between pairs of columns of active areas. Typically, each routing channel contains space for a fixed number of leads, i.e. routing tracks, which run on top of oxide isolation regions formed between the pairs of columns. To promote standardization and flexibility in implementing multiple functions within one substrate layout, generally the same number of routing tracks are allocated to each routing channel within the array.
An improvement on this type of prior art array is shown in U.S. Pat. No. 4,884,118 entitled, Double Metal HCMOS Compacted Array, assigned to LSI Logic Corporation. In this embodiment, active areas are arranged in adjacent columns of alternating conductivity types with no intervening area allocated for metal routing. The placement of alternating conductivity type columns allows for the formation of CMOS type devices in which the P-type regions are on either the right or left sides of the devices depending upon the needs of the circuit.
Thus, in a CMOS circuit application, if some substrate area must be left unused in order to allow for the most efficient placement of routing channels, less substrate area need be wasted in the overall layout since the next CMOS device may begin at the next column either n-type or p-type whichever is available.
This prior art method has a high flexibility of circuit design by allowing increments of a single column to be dedicated to routing. This core array design however, has the disadvantage of requiring a symmetrical array, that is, a p channel lying adjacent to an n-channel. This disadvantage manifests itself in several ways. A gate array using the prior art structure described in the above mentioned patent requires at least one contact point that is dedicated to the connection of the substrate taps between the active areas.
In addition to the alternating nature of the active regions, there is a distinct possibility that there has to be extensive routing of the wires in the integrated circuit when providing the personality layer to provide the desired logical structure described in the above-mentioned patent.
The type of logic array described in the above mentioned patent has a core cell of eight transistors which include two substrate taps therebetween. Typically in the prior art cell described in the above mentioned patent, what is shown is an active area with a first pair of p-channel transistors on one side, a second pair of p-channel transistors on a second side and a substrate tap therebetween. This prior art cell includes a second active area with a first pair of n-channel transistors on one side, a second pair of n-channel transistor on a second side and a substrate tap therebetween. The substrate taps provide the P-channel and N-channel substrate with a voltage potential.
The disadvantage of the substrate tap being between p or n channel transistors is gate density (i.e. number of gates per sq.mm). The diffusion spacing between the substrate taps and transistor diffusion is greater than that of the polysilicon. Secondly, the alternating configuration is inefficient at the chip level in random access memory (RAM) or read-only memory (ROM) implementations when the layout is a complex bus structure.
Typically this type of cell is utilized to provide multiple columns of active areas to provide the gate array architecture. This cell has the further disadvantage of requiring the jumping of a column when connections must be made between columns of the same conductivity type. For example in the case when two p-channel and one n-channel are used to form a cell i.e. p-p-n, the p-channel has half the speed of an n-channel and two p-channel will give a more balanced propagation delay. This adds significant complexity to the routing of these connections. Finally due to the alternating nature of the columns and position of the substrate tap (between the transistors), routing of the voltage potential lines and other metal connections can also become quite complex.
Often times, testability is also a problem in such devices. That is, often times it is difficult to test all of the outputs of the gate array. There are known boundary scan techniques that are relatively complex. Typically in such gate array architectures, such boundary scan techniques are not cost effective for many applications
The present invention overcomes the above-mentioned problems with testability and density problems with gate array cells. In addition, the gate array geometry of the present invention accommodates an optimum circuit layout with minimum waste of silicon area and also accommodates efficient implementation of the personality layers required for the desired logical design.